The present invention relates to a semiconductor storage device including a dynamic random access memory circuit and the like, and more particularly, it relates to a semiconductor storage device comprising memory cells each including two transistors and one storage capacitor.
A low latency DRAM cell of a dual word line and dual bit line system disclosed in U.S. Pat. Nos. 5,856,940, 5,963,468 and 5,963,497, in which each memory cell is provided with two transistors and one storage capacitor and is connected with two word lines and two bit lines, will now be described with reference to a drawing.
FIG. 7 shows the circuit configuration of a memory cell of a semiconductor storage device including the conventional low latency DRAM cell. The memory cell 10 of FIG. 7 includes, for example, a first switch transistor 102 that is connected with a first word line WL0A at its gate, with a first bit line BL0A at its drain and with a storage node 101 at its source; a source switch transistor 103 that is connected with a second word line WL0B at its gate, with a second bit line BL0B at its drain and with the storage node 101 at its source; and a storage capacitor 104 that is connected with the storage node 101 at one electrode and uses a cell plate as the other electrode.
In this manner, the memory cell 100 includes the first switch transistor 102 and the second switch transistor 103 independently controllable with respect to one storage capacitor 104. Accordingly, an interleaving operation can be conducted between a combination of the first word line WL0A and the first bit line BL0A and a combination of the second word line WL0B and the second bit line BL0B all extending over plural memory cells 100, resulting in rapid read and write operations.
In the semiconductor storage device including the conventional low latency DRAM cells, however, the interleaving operation is conducted on bit lines adjacent to each other. Therefore, when first bit lines BLnA and second bit lines BLnB (wherein n is 0 or a larger integer) are operated independently of each other, a coupling noise derived from change of a bit line potential caused during the operation can be disadvantageously introduced into an adjacent bit line. In the worst case, the introduction of such a coupling noise can cause inversion of a data value held by the memory cell 100.